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| PSoC(R) Mixed-Signal Array CY8C29466, CY8C29566, CY8C29666, and CY8C29866 Final Data Sheet Features Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz Two 8x8 Multiply, 32-Bit Accumulate Low Power at High Speed 3.0V to 5.25V Operating Voltage Operating Voltages Down to 1.0V Using OnChip Switch Mode Pump (SMP) Industrial Temperature Range: -40C to +85C Advanced Peripherals (PSoC Blocks) 12 Rail-to-Rail Analog PSoC Blocks Provide: - Up to 14-Bit ADCs - Up to 9-Bit DACs - Programmable Gain Amplifiers - Programmable Filters and Comparators 16 Digital PSoC Blocks Provide: - 8- to 32-Bit Timers, Counters, and PWMs - CRC and PRS Modules - Up to 4 Full-Duplex UARTs - Multiple SPITM Masters or Slaves - Connectable to all GPIO Pins Complex Peripherals by Combining Blocks Precision, Programmable Clocking Internal 2.5% 24/48 MHz Oscillator 24/48 MHz with Optional 32.768 kHz Crystal Optional External Oscillator, up to 24 MHz Internal Oscillator for Watchdog and Sleep Flexible On-Chip Memory 32K Bytes Flash Program Storage 50,000 Erase/Write Cycles 2K Bytes SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Programmable Pin Configurations 25 mA Sink on all GPIO Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO Up to 12 Analog Inputs on GPIO Four 40 mA Analog Outputs on GPIO Configurable Interrupt on all GPIO Additional System Resources I2CTM Slave, Master, and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Complete Development Tools Free Development Software (PSoC DesignerTM) Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory Complex Events C Compilers, Assembler, and Linker Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers PSoC(R) Functional Overview The PSoC(R) family consists of many Mixed-Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages. The PSoC architecture, as illustrated on the left, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C29x66 family can have up to eight IO ports that connect to the global digital and analog interconnects, providing access to 16 digital blocks and 12 analog blocks. SYSTEM BUS Global Digital Interconnect SRAM 2K Interrupt Controller Global Analog Interconnect Flash 32K SROM PSoC CORE Sleep and Watchdog CPUCore (M8C) Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array ANALOG SYSTEM Analog Ref. Analog Block Array Analog Input Muxing The PSoC Core The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 25 vec- Digital Clocks Two Multiply Accums. POR and LVD Decimator I 2C System Resets Internal Voltage Ref. Switch Mode Pump SYSTEM RESOURCES February 15, 2007 (c) Cypress Semiconductor 2003-2007 -- Document No. 38-12013 Rev. *H 1 [+] Feedback CY8C29x66 Final Data Sheet PSoC(R) Overview tors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 32 KB of Flash for program storage, 2 KB of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. Digital System Block Diagram Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Digital Clocks FromCore To System Bus ToAnalog System DIGITAL SYSTEM Digital PSoC Block Array Row Input Configuration Row 0 DBB00 DBB01 DCB02 4 DCB03 4 Row Output Configuration 8 8 Row Input Configuration 8 Row 1 DBB10 DBB11 DCB12 4 DCB13 4 8 Row Output Configuration Row Input Configuration Row 2 DBB20 DBB21 DCB22 4 DCB23 4 Row Output Configuration Row Input Configuration The Digital System The Digital System is composed of 16 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital peripheral configurations include those listed below. Row 3 DBB30 DBB31 DCB32 4 DCB33 4 Row Output Configuration GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] PWMs (8 to 32 bit) PWMs with Dead band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity (up to 4) SPI master and slave (up to 4 each) I2C slave and multi-master (1 available as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA (up to 4) Pseudo Random Sequence Generators (8 to 32 bit) The Analog System The Analog System is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are listed below. Analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch) Amplifiers (up to 4, with selectable gain to 48x) Instrumentation amplifiers (up to 2, with selectable gain to 93x) Comparators (up to 4, with 16 selectable thresholds) DACs (up to 4, with 6- to 9-bit resolution) Multiplying DACs (up to 4, with 6- to 9-bit resolution) High current output drivers (four with 40 mA drive as a Core Resource) 1.3V reference (as a System Resource) The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled PSoC Device Characteristics on page 3. February 15, 2007 Document No. 38-12013 Rev. *H 2 [+] Feedback CY8C29x66 Final Data Sheet PSoC(R) Overview DTMF Dialer Modulators Correlators Peak Detectors Many other topologies possible Additional System Resources System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Statements describing the merits of each system resource are presented below. Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in the figure below. Analog System Block Diagram P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. The decimator provides a custom hardware filter for digital signal, processing applications including the creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter. P0[4] P0[2] P0[0] P2[6] P2[3] P2[4] P2[2] P2[0] P2[1] Array Input Configuration PSoC Device Characteristics ACI3[1:0] ACI0[1:0] ACI1[1:0] ACI2[1:0] Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is highlighted below. PSoC Device Characteristics Analog Columns Block Array ACB00 ASC10 ASD20 ACB01 ASD11 ASC21 ACB02 ASC12 ASD22 ACB03 Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital IO Digital Rows SRAM Size 2K 256 Bytes 1K 256 Bytes 512 Bytes 256 Bytes 512 Bytes ASD13 ASC23 PSoC Part Number CY8C29x66 CY8C27x43 up to 64 up to 44 56 up to 24 up to 28 16 up to 28 4 2 1 1 1 1 0 16 8 4 4 4 4 0 12 12 48 12 28 8 28 4 4 2 2 0 0 0 4 4 2 2 2 2 0 12 12 6 6 4a 4a 3b Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap CY8C24x94 CY8C24x23A CY8C21x34 CY8C21x23 M8C Interface (Address Bus, Data Bus, Etc.) CY8C20x34 a. Limited analog functionality. b. Two analog blocks and one CapSense. February 15, 2007 Document No. 38-12013 Rev. *H Flash Size 32K 16K 16K 4K 8K 4K 8K 3 [+] Feedback CY8C29x66 Final Data Sheet PSoC(R) Overview Getting Started The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoC Mixed-Signal Array Technical Reference Manual. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at http://www.cypress.com/psoc. Development Tools PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-onChip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.) PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family. PSoC Designer Subsystems Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store at http://www.onfulfillment.com/cypressstore/ contains development kits, C compilers, and all accessories for PSoC development. Click on PSoC (Programmable System-on-Chip) to view a current list of available items. Technical Training Modules Free PSoC technical training modules are available for users new to PSoC. Training modules cover designing, debugging, advanced analog and CapSense. Go to http:// www.cypress.com/techtrain. PSoC Designer Graphical Designer Interface Context Sensitive Help Commands Results Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant, go to the following Cypress support web site: http://www.cypress.com/support/cypros.cfm. Importable Design Database Device Database Application Database Project Database User Modules Library PSoC Configuration Sheet Technical Support PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm. PSoC Designer Core Engine Manufacturing Information File Application Notes A long list of application notes will assist you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are listed by date by default. Emulation Pod In-Circuit Emulator Device Programmer February 15, 2007 Document No. 38-12013 Rev. *H 4 [+] Feedback CY8C29x66 Final Data Sheet PSoC(R) Overview PSoC Designer Software Subsystems Device Editor The Device Editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It's also possible to change the selected components and regenerate the framework. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Hardware Tools In-Circuit Emulator Design Browser The Design Browser allows users to select and import preconfigured designs into the user's project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader. A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of the USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Application Editor In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports Cypress' PSoC family devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. February 15, 2007 Document No. 38-12013 Rev. *H 5 [+] Feedback CY8C29x66 Final Data Sheet PSoC(R) Overview Designing with User Modules The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses, and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements. To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides highlevel functions to control and respond to hardware events at run-time. The API also provides optional interrupt service routines that you can adapt as needed. The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions. User Module and Source Code Development Flows Device Editor User Module Selection Placement and Parameter -ization Source Code Generator Generate Application Application Editor Project Manager Source Code Editor Build Manager Build All Debugger Interface to ICE Storage Inspector Event & Breakpoint Manager The next step is to write your main program, and any sub-routines using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive "grep-style" patterns. A single mouse click invokes the Build Manager. It employs a professional-strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. February 15, 2007 Document No. 38-12013 Rev. *H 6 [+] Feedback CY8C29x66 Final Data Sheet PSoC(R) Overview Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Acronym AC ADC API CPU CT DAC DC ECO EEPROM FSR GPIO GUI HBM ICE ILO IMO IO IPOR LSb LVD MSb PC PLL POR PPOR PSoCTM PWM SC SLIMO SMP SRAM alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose IO graphical user interface human body model in-circuit emulator internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset Programmable System-on-ChipTM pulse width modulator switched capacitor slow IMO switch mode pump static random access memory Description Table of Contents For an in depth discussion and more information on your PSoC device, obtain the PSoC Mixed Signal Array Technical Reference Manual. This document encompasses and is organized into the following chapters and sections. 1. Pin Information ........................................................................................ 8 1.1 Pinouts ........................................................................................... 8 1.1.1 28-Pin Part Pinout ........................................................... 8 1.1.2 44-Pin Part Pinout ........................................................... 9 1.1.3 48-Pin Part Pinouts ....................................................... 10 1.1.4 100-Pin Part Pinout ....................................................... 12 1.1.5 100-Pin Part Pinout (On-Chip Debug) ........................... 14 Register Reference ................................................................................ 16 2.1 Register Conventions ................................................................... 16 2.1.1 Abbreviations Used ....................................................... 16 2.2 Register Mapping Tables ............................................................. 16 Electrical Specifications ....................................................................... 19 3.1 Absolute Maximum Ratings ......................................................... 20 3.2 Operating Temperature ................................................................ 20 3.3 DC Electrical Characteristics ........................................................ 21 3.3.1 DC Chip-Level Specifications ........................................ 21 3.3.2 DC General Purpose IO Specifications ......................... 21 3.3.3 DC Operational Amplifier Specifications ....................... 22 3.3.4 DC Low Power Comparator Specifications ................... 23 3.3.5 DC Analog Output Buffer Specifications ....................... 24 3.3.6 DC Switch Mode Pump Specifications .......................... 25 3.3.7 DC Analog Reference Specifications ............................ 26 3.3.8 DC Analog PSoC Block Specifications .......................... 27 3.3.9 DC POR, SMP, and LVD Specifications ....................... 27 3.3.10 DC Programming Specifications ................................... 28 3.4 AC Electrical Characteristics ........................................................ 29 3.4.1 AC Chip-Level Specifications ........................................ 29 3.4.2 AC General Purpose IO Specifications ......................... 31 3.4.3 AC Operational Amplifier Specifications ........................ 32 3.4.4 AC Low Power Comparator Specifications ................... 34 3.4.5 AC Digital Block Specifications ..................................... 34 3.4.6 AC Analog Output Buffer Specifications ........................ 35 3.4.7 AC External Clock Specifications .................................. 36 3.4.8 AC Programming Specifications .................................... 36 3.4.9 AC I2C Specifications .................................................... 37 Packaging Information .......................................................................... 38 4.1 Packaging Dimensions ................................................................. 38 4.2 Thermal Impedances ................................................................... 42 4.3 Capacitance on Crystal Pins ........................................................ 43 4.4 Solder Reflow Peak Temperature ................................................ 43 Development Tool Selection ................................................................ 44 5.1 Software ....................................................................................... 44 5.1.1 PSoC Designer .............................................................. 44 5.1.2 PSoC Express ............................................................... 44 5.1.3 PSoC Programmer ........................................................ 44 5.1.4 CY3202-C iMAGEcraft C Compiler ............................... 44 5.2 Development Kits ......................................................................... 44 5.2.1 CY3215-DK Basic Development Kit .............................. 44 5.2.2 CY3210-ExpressDK Development Kit ........................... 45 5.3 Evaluation Tools ........................................................................... 45 5.3.1 CY3210-MiniProg1 ........................................................ 45 5.3.2 CY3210-PSoCEval1 ...................................................... 45 5.3.3 CY3214-PSoCEvalUSB ................................................ 45 5.4 Device Programmers ................................................................... 45 5.4.1 CY3216 Modular Programmer ...................................... 45 5.4.2 CY3207ISSP In-System Serial Programmer (ISSP) ..... 45 5.5 Accessories (Emulation and Programming) ................................. 46 5.6 3rd-Party Tools ............................................................................. 46 5.7 Build a PSoC Emulator into Your Board ...................................... 46 Ordering Information ............................................................................ 47 6.1 Ordering Code Definitions ............................................................ 47 Sales and Service Information ............................................................. 48 7.1 Revision History ........................................................................... 48 7.2 Copyrights and Code Protection .................................................. 48 2. 3. 4. 5. Units of Measure A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 19 lists all the abbreviations used to measure the PSoC devices. Numeric Naming Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexidecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (e.g., 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal. 6. 7. February 15, 2007 Document No. 38-12013 Rev. *H 7 [+] Feedback 1. Pin Information This chapter describes, lists, and illustrates the CY8C29x66 PSoC device pins and pinout configurations. 1.1 Pinouts The CY8C29x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a "P") is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 1.1.1 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 28-Pin Part Pinout Type Table 1-1. 28-Pin Part Pinout (PDIP, SSOP, SOIC) Digital IO IO IO IO IO IO IO IO Power IO IO IO IO Power IO IO IO IO Input IO IO IO IO IO IO IO IO Power I I Analog I IO IO I Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] SMP P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Description Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. CY8C29466 28-Pin PSoC Device A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] SMP I2CSCL,P1[7] I2CSDA, P1[5] P1[3] I2CSCL,XTALin, P1[1] Vss I I Direct switched capacitor block input. Direct switched capacitor block input. Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VREF). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PDIP SSOP SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6],ExternalVREF P2[4],ExternalAGND P2[2], A, I P2[0], A, I XRES P1[6] P1[4],EXTCLK P1[2] P1[0],XTALout,I2CSDA I IO IO I LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details. February 15, 2007 Document No. 38-12013 Rev. *H 8 [+] Feedback CY8C29x66 Final Data Sheet 1. Pin Information 1.1.2 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin Part Pinout Type Table 1-2. 44-Pin Part Pinout (TQFP) Digital IO IO IO IO IO IO IO Power IO IO IO IO IO IO IO IO Power IO IO IO IO IO IO IO IO Input IO IO IO IO IO IO IO IO IO IO IO IO Power IO IO IO IO IO I IO IO I Analog I I Pin Name P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] P0[1] P2[7] Description Direct switched capacitor block input. Direct switched capacitor block input. CY8C29566 44-Pin PSoC Device P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6],ExternalVREF 33 32 31 30 29 28 27 26 25 24 23 P2[4],External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. I I I IO IO I Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VREF). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details. February 15, 2007 Document No. 38-12013 Rev. *H P3[1] I2CSCL, P1[7] I2C SDA, P1[5] P1[3] I2CSCL,XTALin,P1[1] Vss I2CSDA,XTALout,P1[0] P1[2] EXTCLK,P1[4] P1[6] P3[0] 12 13 14 15 16 17 18 19 20 21 22 P2[5] A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 P2[7] P0[1], A, I P0[3], A, IO P0[5], A, IO P0[7], A, I Vdd TQFP 9 [+] Feedback CY8C29x66 Final Data Sheet 1. Pin Information 1.1.3 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 48-Pin Part Pinouts Type Table 1-3. 48-Pin Part Pinout (SSOP) Digital IO IO IO IO IO IO IO IO IO IO IO IO Power IO IO IO IO IO IO IO IO IO IO Power IO IO IO IO IO IO IO IO IO IO Input IO IO IO IO IO IO IO IO IO IO IO IO Power Analog I IO IO I Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Description Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. CY8C29666 48-Pin PSoC Device A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2CSCL, P1[7] I2CSDA, P1[5] P1[3] I2CSCL,XTALin,P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 I I Direct switched capacitor block input. Direct switched capacitor block input. Switch Mode Pump (SMP) connection to external components required. SSOP I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6],External VREF P2[4],External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4],EXTCLK P1[2] P1[0],XTALout,I2C SDA Active high external reset with internal pull down. I I I IO IO I Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VREF). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details. February 15, 2007 Document No. 38-12013 Rev. *H 10 [+] Feedback CY8C29x66 Final Data Sheet 1. Pin Information Table 1-4. 48-Pin Part Pinout (QFN**) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Power I IO IO I I IO IO I I I IO IO IO IO IO IO IO IO IO IO Input IO IO IO IO IO IO IO IO IO IO Power Type Digital IO IO IO IO IO IO Power Analog I I Pin Name P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] Description Direct switched capacitor block input. Direct switched capacitor block input. CY8C29666 48-Pin PSoC Device Vdd P0[6], A,I P0[4], A,IO P0[2], A,IO P0[0], A,I P2[6],ExternalVREF 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P2[4],External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VREF). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details. ** The QFN package has a center pad that must be connected to ground (Vss). February 15, 2007 Document No. 38-12013 Rev. *H 13 14 I2CSDA,P1[5] 15 P1[3] 16 I2CSCL,XTALin,P1[1] 17 Vss 18 I2CSDA,XTALout,P1[0] 19 P1[2] 20 EXTCLK,P1[4] 21 P1[6] 22 P5[0] 23 P5[2] 24 A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] 1 2 3 4 5 6 7 8 9 10 11 12 P5[1] I2CSCL,P1[7] 48 47 46 45 44 43 P2[5] P2[7] P0[1], A,I P0[3], A,IO P0[5], A,IO P0[7], A,I QFN (Top View ) 11 [+] Feedback CY8C29x66 Final Data Sheet 1. Pin Information 1.1.4 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100-Pin Part Pinout Type Table 1-5. 100-Pin Part Pinout (TQFP) Digital Analog Name NC NC P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] NC NC SMP Vss P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] NC NC NC P1[5] P1[3] P1[1] NC Vdd NC Vss NC P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4] P1[6] NC NC NC Description No connection. No connection. Analog column mux input. Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Type Digital IO IO IO IO IO IO IO IO Analog Name NC P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] NC NC XRES P4[0] P4[2] No connection. Description IO IO IO IO IO IO IO IO IO I I I Direct switched capacitor block input. Direct switched capacitor block input. No connection. No connection. Switch Mode Pump (SMP) connection to external components required. Ground connection. Input IO IO Power IO IO IO IO IO IO IO I No connection. No connection. Active high external reset with internal pull down. Power Power IO IO IO IO IO IO IO IO IO I I IO IO IO I2C Serial Clock (SCL). No connection. No connection. No connection. I2C Serial Data (SDA). Crystal (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. No connection. Supply voltage. No connection. Ground connection. No connection. IO IO IO IO Vss P4[4] P4[6] P2[0] P2[2] P2[4] NC P2[6] NC P0[0] NC NC P0[2] NC P0[4] NC P0[6] Vdd Vdd Vss Vss P6[0] P6[1] P6[2] P6[3] P6[4] P6[5] P6[6] P6[7] NC P0[7] NC P0[5] NC P0[3] NC Ground connection. Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). No connection. External Voltage Reference (VREF). No connection. Analog column mux input. No connection. No connection. Analog column mux input and column output. No connection. Analog column mux input and column output. No connection. Analog column mux input. Supply voltage. Supply voltage. Ground connection. Ground connection. IO Power Power Power Power IO IO IO IO IO IO IO IO I Power Power IO IO IO IO IO IO IO IO IO IO IO IO Crystal (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). No connection. No connection. No connection. No connection. Analog column mux input. No connection. Analog column mux input and column output. No connection. Analog column mux input and column output. No connection. IO IO IO I IO IO LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details. February 15, 2007 Document No. 38-12013 Rev. *H 12 [+] Feedback CY8C29x66 Final Data Sheet 1. Pin Information CY8C29866 100-Pin PSoC Device NC P0[3], A, IO NC P0[5], A, IO NC P0[7], A, I NC Vdd Vdd P0[6], A, I NC P0[4], A, IO NC P0[2], A, IO NC 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC P0[0], A, I NC P2[6],External VREF NC P2[4],External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] Vss P4[2] P4[0] XRES NC NC P3[6] P3[4] P3[2] P3[0] P5[6] P5[4] P5[2] P5[0] NC February 15, 2007 NC NC I2C SDA, P1[5] P1[3] XTALin,I2CSCL,P1[1] NC Vdd NC Vss NC P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] XTALout,I2CSDA,P1[0] P1[2] EXTCLK,P1[4] P1[6] NC NC NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] NC NC SMP Vss P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] I2C SCL, P1[7] NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 Document No. 38-12013 Rev. *H P6[7] P6[6] P6[5] P6[4] P6[3] P6[2] P6[1] P6[0] Vss Vss TQFP 13 [+] Feedback CY8C29x66 Final Data Sheet 1. Pin Information 1.1.5 100-Pin Part Pinout (On-Chip Debug) The 100-pin TQFP part is for the CY8C29000 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production Table 1-6. 100-Pin Part Pinout (TQFP) Analog Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name Description No connection. No connection. Analog column mux input. Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Analog Digital Digital Name P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] HCLK CCLK XRES P4[0] P4[2] Vss P4[4] P4[6] P2[0] P2[2] P2[4] NC P2[6] NC P0[0] NC NC P0[2] NC P0[4] NC Description NC NC IO I, M P0[1] IO M P2[7] IO M P2[5] IO I, M P2[3] IO I, M P2[1] IO M P4[7] IO M P4[5] IO M P4[3] IO M P4[1] OCDE OCDO NC Power Vss IO M P3[7] IO M P3[5] IO M P3[3] IO M P3[1] IO M P5[7] IO M P5[5] IO M P5[3] IO M P5[1] IO M P1[7] NC NC NC IO P1[5] IO P1[3] IO P1[1] NC Vss D+ DVdd P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] NC NC NC NC P1[0] P1[2] P1[4] Direct switched capacitor block input. Direct switched capacitor block input. IO IO IO IO IO IO IO IO IO M M M M M M M M M OCD even data IO. OCD odd data output. No connection. Ground connection. Input IO M IO M Power IO M IO M IO I, M IO I, M IO IO IO I OCD high-speed clock output. OCD CPU clock output. Active high pin reset with internal pull down. Ground connection. I2C Serial Clock (SCL). No connection. No connection. No connection. I2C Serial Data (SDA) Crystal (XTALin), I2C Serial Clock (SCL), ISSP SCLK*. No connection. Ground connection. IO IO I, M I, M Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input. No connection. External Voltage Reference (VREF) input. No connection. Analog column mux input. No connection. No connection. Analog column mux input and column output. No connection. Analog column mux input and column output. No connection. Analog column mux input. Supply voltage. No connection. Ground connection. No connection. No connection. No connection. No connection. No connection. No connection. No connection. No connection. No connection. No connection. Analog column mux input. No connection. Analog column mux input and column output. No connection. Analog column mux input and column output. No connection. Power USB USB Power IO IO IO IO IO IO IO IO Supply voltage. IO IO IO No connection. No connection. No connection. No connection. Crystal (XTALout), I2C Serial Data (SDA), ISSP SDATA*. Optional External Clock Input (EXTCLK). IO I, M P0[6] Power Vdd NC Power Vss NC NC NC NC NC NC NC NC NC NC IO I, M P0[7] NC IO IO, M P0[5] NC IO IO, M P0[3] NC LEGEND A = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input, OCD = On-Chip Debugger. * These are the ISSP pins, which are not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details. February 15, 2007 Document No. 38-12013 Rev. *H 14 [+] Feedback CY8C29x66 Final Data Sheet 1. Pin Information CY8C29000 OCD P0[3], M, AI NC P0[5], M, AI NC P0[7], M, AI NC NC Vdd P0[6], M, AI NC P0[4], M, AI 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 NC NC AI, M , P0[1] M , P2[7] M , P2[5] AI, M , P2[3] AI, M , P2[1] M , P4[7] M , P4[5] M , P4[3] M , P4[1] OCDE OCDO NC Vss M , P3[7] M , P3[5] M , P3[3] M , P3[1] M , P5[7] M , P5[5] M , P5[3] M , P5[1] I2C SCL, P1[7] NC 77 76 M,P1[2] M,P1[4] NC P0[2], M, AI NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC P0[0], M , AI NC P2[6], M , External VREF NC P2[4], M , External AGND P2[2], M , AI P2[0], M , AI P4[6], M P4[4], M Vss P4[2], M P4[0], M XRES CCLK HCLK P3[6], M P3[4], M P3[2], M P3[0], M P5[6], M P5[4], M P5[2], M P5[0], M P1[6], M 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TQFP 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] NC NC Vss NC NC NC NC NC NC NC NC Not for Production February 15, 2007 Document No. 38-12013 Rev. *H P7[1] P7[0] NC NC NC NC I2C SDA, M, P1[0] NC I2C SDA, M, P1[5] M,P1[3] I2C SCL, M, P1[1] NC Vss D+ DVdd NC 46 47 48 49 50 15 [+] Feedback 2. Register Reference This chapter lists the registers of the CY8C29x66 PSoC device. For detailed register information, reference the PSoC Mixed-Signal Array Technical Reference Manual. 2.1 2.1.1 Register Conventions Abbreviations Used 2.2 Register Mapping Tables The register conventions specific to this section are listed in the following table. Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note In the following register mapping tables, blank fields are reserved and should not be accessed. February 15, 2007 Document No. 38-12013 Rev. *H 16 [+] Feedback CY8C29x66 Final Data Sheet 2. Register Reference Register Map Bank 0 Table: User Space Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name PRT0DR 00 RW DBB20DR0 40 PRT0IE 01 RW DBB20DR1 41 PRT0GS 02 RW DBB20DR2 42 PRT0DM2 03 RW DBB20CR0 43 PRT1DR 04 RW DBB21DR0 44 PRT1IE 05 RW DBB21DR1 45 PRT1GS 06 RW DBB21DR2 46 PRT1DM2 07 RW DBB21CR0 47 PRT2DR 08 RW DCB22DR0 48 PRT2IE 09 RW DCB22DR1 49 PRT2GS 0A RW DCB22DR2 4A PRT2DM2 0B RW DCB22CR0 4B PRT3DR 0C RW DCB23DR0 4C PRT3IE 0D RW DCB23DR1 4D PRT3GS 0E RW DCB23DR2 4E PRT3DM2 0F RW DCB23CR0 4F PRT4DR 10 RW DBB30DR0 50 PRT4IE 11 RW DBB30DR1 51 PRT4GS 12 RW DBB30DR2 52 PRT4DM2 13 RW DBB30CR0 53 PRT5DR 14 RW DBB31DR0 54 PRT5IE 15 RW DBB31DR1 55 PRT5GS 16 RW DBB31DR2 56 PRT5DM2 17 RW DBB31CR0 57 PRT6DR 18 RW DCB32DR0 58 PRT6IE 19 RW DCB32DR1 59 PRT6GS 1A RW DCB32DR2 5A PRT6DM2 1B RW DCB32CR0 5B PRT7DR 1C RW DCB33DR0 5C PRT7IE 1D RW DCB33DR1 5D PRT7GS 1E RW DCB33DR2 5E PRT7DM2 1F RW DCB33CR0 5F DBB00DR0 20 # AMX_IN 60 DBB00DR1 21 W 61 DBB00DR2 22 RW 62 DBB00CR0 23 # ARF_CR 63 DBB01DR0 24 # CMP_CR0 64 DBB01DR1 25 W ASY_CR 65 DBB01DR2 26 RW CMP_CR1 66 DBB01CR0 27 # 67 DCB02DR0 28 # 68 DCB02DR1 29 W 69 DCB02DR2 2A RW 6A DCB02CR0 2B # 6B DCB03DR0 2C # TMP_DR0 6C DCB03DR1 2D W TMP_DR1 6D DCB03DR2 2E RW TMP_DR2 6E DCB03CR0 2F # TMP_DR3 6F DBB10DR0 30 # ACB00CR3 70 DBB10DR1 31 W ACB00CR0 71 DBB10DR2 32 RW ACB00CR1 72 DBB10CR0 33 # ACB00CR2 73 DBB11DR0 34 # ACB01CR3 74 DBB11DR1 35 W ACB01CR0 75 DBB11DR2 36 RW ACB01CR1 76 DBB11CR0 37 # ACB01CR2 77 DCB12DR0 38 # ACB02CR3 78 DCB12DR1 39 W ACB02CR0 79 DCB12DR2 3A RW ACB02CR1 7A DCB12CR0 3B # ACB02CR2 7B DCB13DR0 3C # ACB03CR3 7C DCB13DR1 3D W ACB03CR0 7D DCB13DR2 3E RW ACB03CR1 7E DCB13CR0 3F # ACB03CR2 7F Blank fields are Reserved and should not be accessed. # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # RW RW # # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 MUL1_X A8 MUL1_Y A9 MUL1_DH AA MUL1_DL AB ACC1_DR1 AC ACC1_DR0 AD ACC1_DR3 AE ACC1_DR2 AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific. ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI3RI RDI3SYN RDI3IS RDI3LT0 RDI3LT1 RDI3RO0 RDI3RO1 CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_F CPU_SCR1 CPU_SCR0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW RL # # February 15, 2007 Document No. 38-12013 Rev. *H 17 [+] Feedback CY8C29x66 Final Data Sheet 2. Register Reference Register Map Bank 1 Table: Configuration Space Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 PRT6DM0 PRT6DM1 PRT6IC0 PRT6IC1 PRT7DM0 PRT7DM1 PRT7IC0 PRT7IC1 DBB00FN DBB00IN DBB00OU Name Name Name 00 RW DBB20FN 40 01 RW DBB20IN 41 02 RW DBB20OU 42 03 RW 43 04 RW DBB21FN 44 05 RW DBB21IN 45 06 RW DBB21OU 46 07 RW 47 08 RW DCB22FN 48 09 RW DCB22IN 49 0A RW DCB22OU 4A 0B RW 4B 0C RW DCB23FN 4C 0D RW DCB23IN 4D 0E RW DCB23OU 4E 0F RW 4F 10 RW DBB30FN 50 11 RW DBB30IN 51 12 RW DBB30OU 52 13 RW 53 14 RW DBB31FN 54 15 RW DBB31IN 55 16 RW DBB31OU 56 17 RW 57 18 RW DCB32FN 58 19 RW DCB32IN 59 1A RW DCB32OU 5A 1B RW 5B 1C RW DCB33FN 5C 1D RW DCB33IN 5D 1E RW DCB33OU 5E 1F RW 5F 20 RW CLK_CR0 60 21 RW CLK_CR1 61 22 RW ABF_CR0 62 23 AMD_CR0 63 DBB01FN 24 RW 64 DBB01IN 25 RW 65 DBB01OU 26 RW AMD_CR1 66 27 ALT_CR0 67 DCB02FN 28 RW ALT_CR1 68 DCB02IN 29 RW CLK_CR2 69 DCB02OU 2A RW 6A 2B 6B DCB03FN 2C RW TMP_DR0 6C DCB03IN 2D RW TMP_DR1 6D DCB03OU 2E RW TMP_DR2 6E 2F TMP_DR3 6F DBB10FN 30 RW ACB00CR3 70 DBB10IN 31 RW ACB00CR0 71 DBB10OU 32 RW ACB00CR1 72 33 ACB00CR2 73 DBB11FN 34 RW ACB01CR3 74 DBB11IN 35 RW ACB01CR0 75 DBB11OU 36 RW ACB01CR1 76 37 ACB01CR2 77 DCB12FN 38 RW ACB02CR3 78 DCB12IN 39 RW ACB02CR0 79 DCB12OU 3A RW ACB02CR1 7A 3B ACB02CR2 7B DCB13FN 3C RW ACB03CR3 7C DCB13IN 3D RW ACB03CR0 7D DCB13OU 3E RW ACB03CR1 7E 3F ACB03CR2 7F Blank fields are Reserved and should not be accessed. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific. ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW C0 C1 C2 C3 C4 C5 C6 C7 RDI3RI C8 RDI3SYN C9 RDI3IS CA RDI3LT0 CB RDI3LT1 CC RDI3RO0 CD RDI3RO1 CE CF GDI_O_IN D0 GDI_E_IN D1 GDI_O_OU D2 GDI_E_OU D3 D4 D5 D6 D7 D8 D9 DA DB DC OSC_GO_EN DD OSC_CR4 DE OSC_CR3 DF OSC_CR0 E0 OSC_CR1 E1 OSC_CR2 E2 VLT_CR E3 VLT_CMP E4 E5 E6 DEC_CR2 E7 IMO_TR E8 ILO_TR E9 BDG_TR EA ECO_TR EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 CPU_F F7 F8 F9 FLS_PR1 FA FB FC FD CPU_SCR1 FE CPU_SCR0 FF RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R RW W W RW W RL RW # # February 15, 2007 Document No. 38-12013 Rev. *H 18 [+] Feedback 3. Electrical Specifications This chapter presents the DC and AC electrical specifications of the CY8C29x66 PSoC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. Specifications are valid for -40oC TA 85oC and TJ 100oC, except where noted. Refer to Table 3-17 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. Figure 3-1. Voltage versus CPU Frequency Figure 3-1b. IMO Frequency Trim Options S L IM O M o d e =1 4.75 Vdd Voltage 3.00 9 3 kHz C PU F r e q u e n c y 4.75 Vdd Voltage SLIMO Mode = 0 5.25 5.25 S L IM O M o d e =0 The following table lists the units of measure that are used in this chapter. Table 3-1: Units of Measure Symbol o C degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square O l id g V a a tin n r pe g io Re 12 MHz 2 4 MHz 3.60 S L IM O M o d e =1 S L IM O M o d e =0 3.00 9 3 kHz 6 MHz IM O F r e q u e n cy 1 2 MHz 2 4 MHz Unit of Measure Symbol W mA ms mV nA ns nV pA pF pp ppm ps sps V microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak Unit of Measure dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms parts per million picosecond samples per second sigma: one standard deviation volts February 15, 2007 Document No. 38-12013 Rev. *H 19 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications 3.1 Symbol TSTG Absolute Maximum Ratings Description Storage Temperature Min -55 25 Typ Max +100 Units oC Table 3-2: Absolute Maximum Ratings Notes Higher storage temperatures will reduce data retention time. Recommended storage temperature is +25oC 25oC. Extended duration storage temperatures above 65oC will degrade reliability. TA Vdd VIO VIOZ IMIO IMAIO ESD LU Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Maximum Current into any Port Pin Configured as Analog Driver Electro Static Discharge Voltage Latch-up Current -40 -0.5 Vss - 0.5 Vss - 0.5 -25 -50 2000 - - - - - - - - - +85 +6.0 oC V Vdd + 0.5 V Vdd + 0.5 V +50 +50 - 200 mA mA V mA Human Body Model ESD. 3.2 Symbol TA TJ Operating Temperature Description Ambient Temperature Junction Temperature Min -40 -40 - - Typ Max +85 +100 Units oC o Table 3-3: Operating Temperature Notes C The temperature rise from ambient to junction is package specific. See "Thermal Impedances" on page 42. The user must limit the power consumption to comply with this requirement. February 15, 2007 Document No. 38-12013 Rev. *H 20 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications 3.3 3.3.1 DC Electrical Characteristics DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-4: DC Chip-Level Specifications Symbol Vdd IDD Supply Voltage Supply Current Description Min 3.00 - - 8 Typ Max 5.25 14 V mA Units Notes See DC POR and LVD specifications, Table 315 on page 27. Conditions are 5.0V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 0.75 MHz, SYSCLK doubler disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz. Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC TA 55 oC. Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA 85 oC. Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 3.3V, -40 oC TA 55 o IDD3 Supply Current - 5 9 mA IDDP Supply current when IMO = 6 MHz using SLIMO mode. - 2 3 mA ISB ISBH ISBXTL Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, internal slow oscillator, and 32 kHz crystal oscillator active. - - - 3 4 4 10 25 12 A A A C. ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and 32 kHz crystal oscillator active. - 5 27 A Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 3.3V, 55 oC < TA 85 oC. VREF Reference Voltage (Bandgap) 1.28 1.3 1.32 V Trimmed for appropriate Vdd. 3.3.2 DC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-5: DC GPIO Specifications Symbol RPU RPD VOH Pull up Resistor Pull down Resistor High Output Level Description 4 4 Vdd - 1.0 Min Typ 5.6 5.6 - 8 8 - Max Units k k V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget. Vdd = 3.0 to 5.25. Vdd = 3.0 to 5.25. Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Notes VOL Low Output Level - - 0.75 V VIL VIH VH IIL CIN COUT Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output - 2.1 - - - - - - 60 1 3.5 3.5 0.8 V V - - 10 10 mV nA pF pF February 15, 2007 Document No. 38-12013 Rev. *H 21 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications 3.3.3 DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25C and are for design guidance only. Table 3-6: 5V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High TCVOSOA IEBOA CINOA VCMOA CMRROA GOLOA VOHIGHOA VOLOWOA ISOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range. All Cases, except highest. Power = High, Opamp Bias = High Common Mode Rejection Ratio Open Loop Gain High Output Voltage Swing (internal signals) Low Output Voltage Swing (internal signals) Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio - - - - - - 67 150 300 600 1200 2400 4600 80 200 400 800 1600 3200 6400 - A A A A A A dB Vss VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd. - - - - - - 0.0 0.5 60 80 Vdd - .01 - 1.6 1.3 1.2 7.0 200 4.5 - - - - - - 10 8 7.5 35.0 - 9.5 Vdd Vdd - 0.5 - - - 0.1 mV mV mV V/oC pA pF V V dB dB V V Gross tested to 1 A. Package and pin dependent. Temp = 25 oC. Min Typ Max Units Notes February 15, 2007 Document No. 38-12013 Rev. *H 22 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications Table 3-7: 3.3V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High High Power is 5 Volts Only TCVOSOA IEBOA CINOA VCMOA CMRROA GOLOA VOHIGHOA VOLOWOA ISOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Common Mode Rejection Ratio Open Loop Gain High Output Voltage Swing (internal signals) Low Output Voltage Swing (internal signals) Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio - - - - - - 54 150 300 600 1200 2400 - 80 200 400 800 1600 3200 - - dB A A A A A Not Allowed Vss VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd - - - 0 60 80 Vdd - .01 - 7.0 200 4.5 - - - - - 35.0 - 9.5 Vdd - - - .01 V/oC pA pF V dB dB V V Gross tested to 1 A. Package and pin dependent. Temp = 25 oC. - - 1.65 1.32 10 8 mV mV Min Typ Max Units Notes 3.3.4 DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 3-8. DC Low Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC LPC supply current LPC voltage offset Description Low power comparator (LPC) reference voltage range - - Min 0.2 - 10 2.5 Typ 40 30 Max Vdd - 1 V A mV Units Notes February 15, 2007 Document No. 38-12013 Rev. *H 23 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications 3.3.5 DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-9: 5V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High VOHIGHOB High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High PSRROB Supply Voltage Rejection Ratio - - 40 1.1 2.6 64 2 5 - mA mA dB - - - - 0.5 x Vdd - 1.3 0.5 x Vdd - 1.3 V V - - - - 1 1 - - V V - - 0.5 Min 3 +6 - Typ 12 - Vdd - 1.0 Max Units mV V/C V Notes 0.5 x Vdd + 1.3 - 0.5 x Vdd + 1.3 - Table 3-10: 3.3V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High VOHIGHOB High Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High VOLOWOB Low Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High PSRROB Supply Voltage Rejection Ratio - 60 0.8 2.0 64 1 5 - mA mA dB - - - - 0.5 x Vdd - 1.0 0.5 x Vdd - 1.0 V V 0.5 x Vdd + 1.0 - 0.5 x Vdd + 1.0 - - - V V - - - - 10 10 - - 0.5 Min 3 +6 Typ 12 - Vdd - 1.0 Max Units mV V/C V Notes February 15, 2007 Document No. 38-12013 Rev. *H 24 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications 3.3.6 DC Switch Mode Pump Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-11: DC Switch Mode Pump (SMP) Specifications Symbol VPUMP 5V VPUMP 3V IPUMP Description 5V Output Voltage at Vdd from Pump 3V Output Voltage at Vdd from Pump Available Output Current VBAT = 1.5V, VPUMP = 3.25V VBAT = 1.8V, VPUMP = 5.0V VBAT5V VBAT3V VBATSTART VPUMP_Line Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery to Start Pump Line Regulation (over VBAT range) 8 5 1.8 1.0 1.2 - - - - - - - 5.0 3.3 - mA mA V V V Min 4.75 3.00 Typ 5.0 3.25 Max 5.25 3.60 V V Units Notes Configuration of footnote.a Average, neglecting ripple. SMP trip voltage is set to 5.0V. Configuration of footnote.a Average, neglecting ripple. SMP trip voltage is set to 3.25V. Configuration of footnote.a SMP trip voltage is set to 3.25V. SMP trip voltage is set to 5.0V. Configuration of footnote.a SMP trip voltage is set to 5.0V. Configuration of footnote.a SMP trip voltage is set to 3.25V. Configuration of footnote.a 0oC TA 100. 1.25V at TA = 40oC. - 5 - %VO Configuration of footnote.a VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 3-15 on page 27. Configuration of footnote.a VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 3-15 on page 27. Configuration of footnote.a Load is 5 mA. Configuration of footnote.a Load is 5 mA. SMP trip voltage is set to 3.25V. VPUMP_Load Load Regulation - 5 - %VO VPUMP_Ripple Output Voltage Ripple (depends on capaci- - tor/load) E3 FPUMP DCPUMP Efficiency Switching Frequency Switching Duty Cycle 35 - - 100 50 1.4 50 - - - - mVpp % MHz % a. L1 = 2 H inductor, C1 = 10 F capacitor, D1 = Schottky diode. See Figure 3-2. Figure 3-2. Basic Switch Mode Pump Circuit D1 Vdd V PUMP L1 V BAT C1 SMP + Battery PSoC Vss February 15, 2007 Document No. 38-12013 Rev. *H 25 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications 3.3.7 DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 3-12: 5V DC Analog Reference Specifications Symbol VBG5 - - - - - - - - - - - - - - - - - - AGND = Vdd/2a AGND = 2 x BandGap a a a a Description Bandgap Voltage Reference 5V 1.28 Min 1.30 Vdd/2 2.60 P2[4] 1.3 2.08 0.000 Vdd/2 - 0.02 2.52 P2[4] - 0.013 1.27 2.03 -0.034 Typ 1.32 Max V V V V V V V V V V V V V V V V V V V Vdd/2 + 0.02 2.72 P2[4] + 0.013 1.34 2.13 0.034 Units AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap AGND = 1.6 x BandGap AGND Block to Block Variation (AGND = Vdd/2)a RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) RefHi = 2 x BandGap RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Vdd/2 + 1.21 3.75 P2[6] + 2.478 P2[4] + 1.218 P2[4] + P2[6] - 0.058 2.50 4.02 Vdd/2 + 1.3 3.9 P2[6] + 2.6 P2[4] + 1.3 P2[4] + P2[6] 2.60 4.16 Vdd/2 + 1.382 4.05 P2[6] + 2.722 P2[4] + 1.382 P2[4] + P2[6] + 0.058 2.70 4.29 Vdd/2 - 1.369 1.20 2.489 - P2[6] P2[4] - 1.368 P2[4] - P2[6] - 0.042 Vdd/2 - 1.30 1.30 2.6 - P2[6] P2[4] - 1.30 P2[4] - P2[6] Vdd/2 - 1.231 1.40 2.711 - P2[6] P2[4] - 1.232 P2[4] - P2[6] + 0.042 a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V 0.02V. Table 3-13: 3.3V DC Analog Reference Specifications Symbol VBG33 - - - - - - - - - - - - - - - - - - AGND = Vdd/2a AGND = 2 x BandGapa AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGapa AGND = 1.6 x BandGap a a Description Bandgap Voltage Reference 3.3V 1.28 Min 1.30 Vdd/2 Vdd/2 - 0.02 Not Allowed P2[4] - 0.009 1.27 2.03 -0.034 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] - 0.042 2.50 Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed P2[4] - P2[6] - 0.036 P2[4] 1.30 2.08 0.000 Typ 1.32 Max V V Vdd/2 + 0.02 Units P2[4] + 0.009 1.34 2.13 0.034 V V V mV AGND Block to Block Variation (AGND = Vdd/2) RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) RefHi = 2 x BandGap RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] 2.60 P2[4] + P2[6] + 0.042 2.70 V V P2[4] - P2[6] P2[4] - P2[6] + 0.036 V a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V 0.02V. February 15, 2007 Document No. 38-12013 Rev. *H 26 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications 3.3.8 DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-14: DC Analog PSoC Block Specifications Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) - - Min 80 Typ 12.2 - - Max fF Units k Notes 3.3.9 DC POR, SMP, and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-15: DC POR, SMP, and LVD Specifications Symbol VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for SMP Trip VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10 V V V V V V V V V 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98a 3.08 3.20 4.08 4.57 4.74b 4.82 4.91 V V V V V V V V V - - - 92 0 0 - - - mV mV mV - 2.82 4.39 4.55 - V V V - Description Vdd Value for PPOR Trip (positive ramp) 2.91 4.39 4.55 - V V V Min Typ Max Units Notes a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. February 15, 2007 Document No. 38-12013 Rev. *H 27 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications 3.3.10 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-16: DC Programming Specifications Symbol IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Description Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Flash Endurance (per block) Flash Endurance (total) Flash Data Retention a Min - - 2.2 - - - Vdd - 1.0 50,000 1,800,000 10 10 - - - - - - - - - Typ 30 0.8 - 0.2 1.5 Max V V Units mA Notes mA mA Driving internal pull-down resistor. Driving internal pull-down resistor. Vss + 0.75 V Vdd - - - V - - Years Erase/write cycles per block. Erase/write cycles. a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. February 15, 2007 Document No. 38-12013 Rev. *H 28 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications 3.4 3.4.1 AC Electrical Characteristics AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Note See the individual user module data sheets for information on maximum frequencies for user modules. Table 3-17: AC Chip-Level Specifications Symbol FIMO24 Description Internal Main Oscillator Frequency for 24 MHz Min 23.4 24 Typ Max 24.6a,b,c Units MHz Notes Trimmed for 5V or 3.3V operation using factory trim values. See the figure on page 19. SLIMO Mode = 0. Trimmed for 5V or 3.3V operation using factory trim values. See the figure on page 19. SLIMO Mode = 1. FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.75 6 6.35a,b,c MHz FCPU1 FCPU2 F48M F24M F32K1 F32K2 FPLL Jitter24M2 TPLLSLEW TPLLSLEWLOW TOS TOSACC CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency External Crystal Oscillator PLL Frequency 24 MHz Period Jitter (PLL) PLL Lock Time PLL Lock Time for Low Gain Setting External Crystal Oscillator Startup to 1% External Crystal Oscillator Startup to 100 ppm 0.93 0.93 0 0 15 - - - 0.5 0.5 - - 24 12 48 24 32 32.768 23.986 - - - 250 300 24.6a,b 12.3 b,c MHz MHz MHz MHz kHz kHz MHz ps ms ms ms ms The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 uW maximum drive level 32.768 kHz crystal. 3.0V Vdd 5.5V, -40 oC TA 85 oC. Refer to the AC Digital Block Specifications below. 49.2a,b,d 24.6b, d 64 - - 600 10 50 500 600 Accuracy is capacitor and crystal dependent. 50% duty cycle. A multiple (x732) of crystal frequency. Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP 32 kHz Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size 48 MHz Output Frequency 24 MHz Period Jitter (IMO) Maximum frequency of signal on row input or row output. Supply Ramp Time - 10 40 - 46.8 - - 0 100 - 50 50 48.0 600 - - 12.3 - - 60 - 49.2a,c ns s % kHz MHz ps MHz s Trimmed. Utilizing factory trim values. a. b. c. d. 4.75V < Vdd < 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. See the individual user module data sheets for information on maximum frequencies for user modules. February 15, 2007 Document No. 38-12013 Rev. *H 29 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications Figure 3-3. PLL Lock Timing Diagram PLL Enable TPLLSLEW 24 MHz FPLL PLL Gain 0 Figure 3-4. PLL Lock for Low Gain Setting Timing Diagram PLL Enable TPLLSLEWLOW 24 MHz FPLL PLL Gain 1 Figure 3-5. External Crystal Oscillator Startup Timing Diagram 32K Select TOS 32 kHz F32K2 Figure 3-6. 24 MHz Period Jitter (IMO) Timing Diagram Jitter24M1 F 24M Figure 3-7. 32 kHz Period Jitter (ECO) Timing Diagram Jitter32k F 32K2 February 15, 2007 Document No. 38-12013 Rev. *H 30 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications 3.4.2 AC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-18: AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF 0 3 2 10 10 Min - - - 27 22 Typ 18 18 - - Max 12.3 Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.75 to 5.25V, 10% - 90% Vdd = 4.75 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Figure 3-8. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS February 15, 2007 Document No. 38-12013 Rev. *H 31 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications 3.4.3 AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = High and Opamp Bias = High is not supported at 3.3V. Table 3-19: 5V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High TSOA Falling Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High SRROA Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High SRFOA Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High BWOA Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) 0.75 3.1 5.4 - - - - 100 - - - - MHz MHz MHz nV/rt-Hz 0.01 0.5 4.0 - - - - - - V/s V/s V/s 0.15 1.7 6.5 - - - - - - V/s V/s V/s - - - - - - 5.9 0.92 0.72 s s s - - - - - - 3.9 0.72 0.62 s s s Min Typ Max Units Notes Table 3-20: 3.3V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High TSOA Falling Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High SRROA Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High SRFOA Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High BWOA Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) 0.67 2.8 - - - 100 - - - MHz MHz nV/rt-Hz 0.24 1.8 - - - - V/s V/s 0.31 2.7 - - - - V/s V/s - - - - 5.41 0.72 s s - - - - 3.92 0.72 s s Min Typ Max Units Notes February 15, 2007 Document No. 38-12013 Rev. *H 32 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor. Figure 3-9. Typical AGND Noise with P2[4] Bypass dBV/rtHz 10000 0 0.01 0.1 1.0 10 1000 100 0.001 0.01 0.1 Freq (kHz) 1 10 100 At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 3-10. Typical Opamp Noise nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000 100 10 0.001 0.01 0.1 Freq (kHz) 1 10 100 February 15, 2007 Document No. 38-12013 Rev. *H 33 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications 3.4.4 AC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 3-21. AC Low Power Comparator Specifications Symbol TRLPC LPC response time Description - Min - Typ 50 Max Units s Notes 50 mV overdrive comparator reference set within VREFLPC. 3.4.5 AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-22: AC Digital Block Specifications Function All Functions Timer Description Maximum Block Clocking Frequency (> 4.75V) Maximum Block Clocking Frequency (< 4.75V) Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Transmitter Maximum Input Clock Frequency Vdd 4.75V, 2 Stop Bits 20 50 50 - - - - - 50 - - Receiver Maximum Input Clock Frequency Vdd 4.75V, 2 Stop Bits - - a a a Min Typ Max 49.2 24.6 Units MHz MHz ns MHz MHz ns MHz MHz Notes 4.75V < Vdd < 5.25V. 3.0V < Vdd < 4.75V. 50a - - 50a - - - - - - - - - 49.2 24.6 - 49.2 24.6 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. - - - - - - - - - - - - - - - - 49.2 49.2 24.6 8.2 4.1 - 24.6 49.2 24.6 49.2 ns ns ns MHz MHz MHz MHz ns ns MHz MHz MHz MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 4.1 MHz due to 2 x over clocking. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). February 15, 2007 Document No. 38-12013 Rev. *H 34 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications 3.4.6 AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-23: 5V AC Analog Output Buffer Specifications Symbol TROB Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High 300 300 - - - - kHz kHz 0.8 0.8 - - - - MHz MHz 0.55 0.55 - - - - V/s V/s 0.5 0.5 - - - - V/s V/s - - - - 3.4 3.4 s s Description Rising Settling Time to 0.1%, 1V Step, 100pF Load - - - - 4 4 s s Min Typ Max Units Notes Table 3-24: 3.3V AC Analog Output Buffer Specifications Symbol TROB Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High 200 200 - - - - kHz kHz 0.7 0.7 - - - - MHz MHz .4 .4 - - - - V/s V/s .36 .36 - - - - V/s V/s - - - - 4 4 s s Description Rising Settling Time to 0.1%, 1V Step, 100pF Load - - - - 4.7 4.7 s s Min Typ Max Units Notes February 15, 2007 Document No. 38-12013 Rev. *H 35 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications 3.4.7 AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-25: 5V AC External Clock Specifications Symbol FOSCEXT - - - Frequency High Period Low Period Power Up IMO to Switch Description Min 0.093 20.6 20.6 150 - - - - Typ Max 24.6 5300 - - Units MHz ns ns s Notes Table 3-26: 3.3V AC External Clock Specifications Symbol FOSCEXT Description Frequency with CPU Clock divide by 1 Min 0.093 - Typ Max 12.3 Units MHz Notes Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. FOSCEXT Frequency with CPU Clock divide by 2 or greater 0.186 - 24.6 MHz - - - High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch 41.7 41.7 150 - - - 5300 - - ns ns s 3.4.8 AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-27: AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Description 1 1 40 40 0 - - - - Min - - - - - 10 10 - - Typ 20 20 - - 8 - - 45 50 Max Units ns ns ns ns MHz ms ms ns ns Vdd > 3.6 3.0 Vdd 3.6 Notes February 15, 2007 Document No. 38-12013 Rev. *H 36 [+] Feedback CY8C29x66 Final Data Sheet 3. Electrical Specifications 3.4.9 AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-28: AC Characteristics of the I2C SDA and SCL Pins Standard Mode Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Set-up Time for STOP Condition 0 4.0 4.7 4.0 4.7 0 250 4.0 Min - - - - - - - - - Max 100 0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 0 a Fast Mode Min - - - - - - - - 50 Max 400 Units kHz s s s s s ns s s ns Notes Bus Free Time Between a STOP and START Condition 4.7 Pulse Width of spikes are suppressed by the input filter. - a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Figure 3-11. Definition for Timing for Fast/Standard Mode on the I2C Bus SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C Sr P S February 15, 2007 Document No. 38-12013 Rev. *H 37 [+] Feedback 4. Packaging Information This chapter illustrates the packaging specifications for the CY8C29x66 PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. 4.1 Packaging Dimensions Figure 4-1. 28-Lead (300-Mil) Molded DIP 51-85014 *D February 15, 2007 Document No. 38-12013 Rev. *H 38 [+] Feedback CY8C29x66 Final Data Sheet 4. Packaging Information Figure 4-2. 28-Lead (210-Mil) SSOP 51-85079 *C Figure 4-3. 28-Lead (300-Mil) SOIC 51-85026 *D February 15, 2007 Document No. 38-12013 Rev. *H 39 [+] Feedback CY8C29x66 Final Data Sheet 4. Packaging Information Figure 4-4. 44-Lead TQFP 51-85064 *C Figure 4-5. 48-Lead (300-Mil) SSOP 51-85061-C 51-85061 *C February 15, 2007 Document No. 38-12013 Rev. *H 40 [+] Feedback CY8C29x66 Final Data Sheet 4. Packaging Information Figure 4-6. 48-Lead (7x7 mm) QFN 001-12919 *A Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Important Note Pinned vias for thermal conduction are not required for the low-power PSoC device. February 15, 2007 Document No. 38-12013 Rev. *H 41 [+] Feedback CY8C29x66 Final Data Sheet 4. Packaging Information Figure 4-7. 100-Lead TQFP 51-85048 ** 51-85048 *C 4.2 Thermal Impedances Package 28 PDIP 28 SSOP 28 SOIC 44 TQFP 48 SSOP 48 QFN** 100 TQFP Typical o Table 4-1. Thermal Impedances per Package JA * 69 C/W 94 oC/W 67 oC/W 60 oC/W 69 oC/W 28 oC/W 50 oC/W * TJ = TA + POWER x JA ** To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane. February 15, 2007 Document No. 38-12013 Rev. *H 42 [+] Feedback CY8C29x66 Final Data Sheet 4. Packaging Information 4.3 Capacitance on Crystal Pins Package 28 PDIP 28 SSOP 28 SOIC 44 TQFP 48 SSOP 48 QFN 100 TQFP Package Capacitance 3.5 pF 2.8 pF 2.7 pF 2.6 pF 3.3 pF 1.8 pF 3.1 pF Table 4-2: Typical Package Capacitance on Crystal Pins 4.4 Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 4-3. Solder Reflow Peak Temperature Package 28 PDIP 28 SSOP 28 SOIC 44 TQFP 48 SSOP 48 QFN 100 TQFP Minimum Peak Temperature* 220oC 240oC 220oC 220oC 220oC 220oC 220oC Maximum Peak Temperature 260oC 260oC 260oC 260oC 260oC 260oC 260oC *Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5oC with Sn-Pb or 245 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. February 15, 2007 Document No. 38-12013 Rev. *H 43 [+] Feedback 5. Development Tool Selection This chapter presents the development tools available for all current PSoC device families including the CY8C29x66 family. 5.1 5.1.1 Software PSoC DesignerTM 5.2 Development Kits All development kits can be purchased from the Cypress Online Store. At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http:// www.cypress.com under DESIGN RESOURCES >> Software and Drivers. 5.2.1 CY3215-DK Basic Development Kit 5.1.2 PSoC ExpressTM The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes: PSoC Designer Software CD ICE-Cube In-Circuit Emulator ICE Flex-Pod for CY8C29x66 Family Cat-5 Adapter Mini-Eval Programming Board 110 ~ 240V Power Supply, Euro-Plug Adapter iMAGEcraft C Compiler (Registration Required) ISSP Cable USB 2.0 Cable and Blue Cat-5 Cable 2 CY8C29466-24PXI 28-PDIP Chip Samples As the newest addition to the PSoC development software suite, PSoC Express is the first visual embedded system design tool that allows a user to create an entire PSoC project and generate a schematic, BOM, and data sheet without writing a single line of code. Users work directly with application objects such as LEDs, switches, sensors, and fans. PSoC Express is available free of charge at http://www.cypress.com/psocexpress. 5.1.3 PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube InCircuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocprogrammer. 5.1.4 CY3202-C iMAGEcraft C Compiler CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. It can be purchased from the Cypress Online Store. At http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items. February 15, 2007 Document No. 38-12013 Rev. *H 44 [+] Feedback CY8C29x66 Final Data Sheet 5. Development Tool Selection 5.2.2 CY3210-ExpressDK PSoC Express Development Kit 5.3.3 CY3214-PSoCEvalUSB The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (may be used with ICE-Cube In-Circuit Emulator). It provides access to I2C buses, voltage reference, switches, upgradeable modules and more. The kit includes: PSoC Express Software CD Express Development Board 4 Fan Modules 2 Proto Modules MiniProg In-System Serial Programmer MiniEval PCB Evaluation Board Jumper Wire Kit USB 2.0 Cable Serial Cable (DB9) 110 ~ 240V Power Supply, Euro-Plug Adapter 2 CY8C24423A-24PXI 28-PDIP Chip Samples 2 CY8C27443-24PXI 28-PDIP Chip Samples 2 CY8C29466-24PXI 28-PDIP Chip Samples The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes: PSoCEvalUSB Board LCD Module MIniProg Programming Unit Mini USB Cable PSoC Designer and Example Projects CD Getting Started Guide Wire Pack 5.4 Device Programmers All device programmers can be purchased from the Cypress Online Store. 5.4.1 CY3216 Modular Programmer 5.3 Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store. The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: Modular Programmer Base 3 Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD Getting Started Guide USB 2.0 Cable 5.3.1 CY3210-MiniProg1 The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable 5.4.2 CY3207ISSP In-System Serial Programmer (ISSP) 5.3.2 CY3210-PSoCEval1 The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note: CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable February 15, 2007 Document No. 38-12013 Rev. *H 45 [+] Feedback CY8C29x66 Final Data Sheet 5. Development Tool Selection 5.5 Accessories (Emulation and Programming) Pin Package 28 PDIP 28 SSOP 28 SOIC 44 TQFP 48 SSOP 48 QFN 100 TQFP Flex-Pod Kita CY3250-29XXX CY3250-29XXX CY3250-29XXX CY3250-29XXX CY3250-29XXX CY325029XXXQFN CY3250-29XXX Foot Kitb CY325028PDIP-FK CY325028SSOP-FK CY325028SOIC-FK CY325044TQFP-FK CY325048SSOP-FK CY325048QFN-FK CY3250100TQFP-FK Adapters can be found at http:// www.emulation.com. Adapterc Table 5-1. Emulation and Programming Accessories Part # CY8C29466 -24PXI CY8C29466 -24PVXI CY8C29466 -24SXI CY8C29566 -24AXI CY8C29666 -24PVXI CY8C29666 -24LFXI CY8C29866 -24AXI a. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. b. Foot kit includes surface mount feet that can be soldered to the target PCB. c. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. 5.6 3rd-Party Tools Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards. 5.7 Build a PSoC Emulator into Your Board For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note "Debugging - Build a PSoC Emulator into Your Board - AN2323" at http://www.cypress.com/ an2323. February 15, 2007 Document No. 38-12013 Rev. *H 46 [+] Feedback 6. Ordering Information The following table lists the CY8C29x66 PSoC devices' key package features and ordering codes. Table 6-1. CY8C29x66 PSoC Device Key Features and Ordering Information Analog PSoC Blocks Switch Mode Pump Temperature Range Digital PSoC Blocks XRES Pin Digital IO Pins Ordering Code Package Analog Outputs Flash (Bytes) RAM (Bytes) Analog Inputs 28 Pin (300 Mil) DIP 28 Pin (210 Mil) SSOP 28 Pin (210 Mil) SSOP (Tape and Reel) 28 Pin (300 Mil) SOIC 28 Pin (300 Mil) SOIC (Tape and Reel) 44 Pin TQFP 44 Pin TQFP (Tape and Reel) 48 Pin (300 Mil) SSOP 48 Pin (300 Mil) SSOP (Tape and Reel) 48 Pin QFN 100 Pin TQFP 100 Pin OCD TQFPa CY8C29466-24PXI CY8C29466-24PVXI CY8C29466-24PVXIT CY8C29466-24SXI CY8C29466-24SXIT CY8C29566-24AXI CY8C29566-24AXIT CY8C29666-24PVXI CY8C29666-24PVXIT CY8C29666-24LFXI CY8C29866-24AXI CY8C29000-24AXI 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 2K 2K 2K 2K 2K 2K 2K 2K 2K 2K 2K 2K Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 16 16 16 16 16 16 16 16 16 16 16 16 12 12 12 12 12 12 12 12 12 12 12 12 24 24 24 24 24 40 40 44 44 44 64 64 12 12 12 12 12 12 12 12 12 12 12 12 4 4 4 4 4 4 4 4 4 4 4 4 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes a. This part may be used for in-circuit debugging. It is NOT available for production. 6.1 Ordering Code Definitions CY 8 C 29 xxx-SPxx Package Type: Thermal Rating: PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX = QFN Pb-Free AX = TQFP Pb-Free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress February 15, 2007 Document No. 38-12013 Rev. *H 47 [+] Feedback 7. Sales and Service Information To obtain information about Cypress Semiconductor or PSoC sales and technical support, reference the following information. Cypress Semiconductor 198 Champion Court San Jose, CA 95134 408.943.2600 Web Sites: Company Information - http://www.cypress.com Sales - http://www.cypress.com/aboutus/sales_locations.cfm Technical Support - http://www.cypress.com/support/login.cfm 7.1 Revision History CY8C29466, CY8C29566, CY8C29666, and CY8C29866 PSoC Mixed-Signal Array Final Data Sheet 38-12013 Issue Date 11/13/2003 01/21/2004 01/27/2004 02/09/2004 06/01/2004 See ECN See ECN See ECN See ECN Origin of Change New Silicon NWJ NWJ SFV SFV SFV SFV HMT HMT New document (Revision **). New information. First edition of preliminary data sheet. Changed part numbers, increased SRAM data storage to 2K bytes. Changed part numbers and removed a 28-pin SOIC. Changes to Overview section, 48-pin MLF pinout, and significant changes to the Electrical Specs. Added a 28-lead (300 mil) SOIC part. New information added to the Electrical Specifications chapter. Add DS standards, update device table, fine-tune pinouts, add Reflow Peak Temp. table. Finalize. Add QFN package clarifications. Add new QFN diagram. Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add CY8C20x34 to PSoC Device Characteristics table. Update emulation pod/feet kit part numbers. Add OCD non-production pinouts and package diagrams. Add ISSP note to pinout tables. Update package diagram revisions. Update typical and recommended Storage Temperature per industrial specs. Update CY branding and QFN convention. Add new Dev. Tool section. Update copyright and trademarks. Description of Change ECN # 131151 132848 133205 133656 227240 240108 247492 288849 722736 Table 7-1. CY8C29X66 Data Sheet Revision History Document Title: Document Number: Revision ** *A *B *C *D *E *F *G *H Distribution: External/Public Posting: None 7.2 Copyrights and Code Protection (c) Cypress Semiconductor Corporation. 2003-2007. All rights reserved. PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress Semiconductor. Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices. Cypress Semiconductor products meet the specifications contained in their particular Cypress Semiconductor Data Sheets. Cypress Semiconductor believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress Semiconductor are committed to continuously improving the code protection features of our products. February 15, 2007 (c) Cypress Semiconductor 2003-2007 -- Document No. 38-12013 Rev. *H 48 [+] Feedback |
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